I just got back from the Design Automation Conference in San Francisco. It is one of the major EDA conferences. Andreas Olofsson gave a talk about the silicon compiler. There was serious discussion about open source EDA. As far as I could tell it is still unclear what the role of academia will be. It seems tricky to align academic incentives with the implementation, and most importantly, maintenance of an open source EDA stack. However, there is quite some buzz and people are enthused. A first workshop, the "Workshop on Open-Source EDA Technology" (WOSET) has been organized.
I also thought I'd try to answer some questions that I've seen in the comments. Disclaimer: as a lowly PhD student I am only privy to some information. I'm answering to the best of my knowledge.
1) As mentioned by hardwarefriend, synthesis tools are standard in ASIC/FPGA design flows. However, chip design currently often still takes a lot of manual work and/or stitching together of tools. The main goal of the compiler is to create a push-button solution. Designing a new chip should be as simple as cloning a design from GitHub and calling "make" on the silicon compiler.
2) Related to (1). The focus is on automation rather than performance. We are okay with sacrificing performance as long as compiler users don't have to deal with individual build steps.
3) There should be support for both digital, analog, and mixed-signal designs.
4) Rest assured that people are aware of yosys and related tools. In fact, Clifford was present at the event :-) Other (academic) open source EDA tools include the ABC for logic synthesis & verification, the EPFL logic synthesis libraries (disclaimer: co-author), and Rsyn for physicial design. There are many others, I'm certainly not familiar with all of them. Compiling a library of available open source tools is part of the project.
Edit: to be clear, WOSET has been planned, but will be held in November. Submissions are open until August 15.
> Compiling a library of available open source tools is part of the project.
Compiling? What's that even mean? What about funding?
I wrote arachne-pnr, the place and route tool for the icestorm stack. My situation changed, I didn't see a way to fund myself to work on it and I didn't have the time to work on it in my spare time. I assume that's one of the reasons Clifford is planning to use VPR going forward (that, and it is almost certainly more mature, has institutional support at Toronto, etc.) I would have loved to work on EDA tools. I've moved on to other things, but I wonder if these programs will fund the likes of Yosys/SymbiFlow/icestorm/arachne-pnr.
I also thought I'd try to answer some questions that I've seen in the comments. Disclaimer: as a lowly PhD student I am only privy to some information. I'm answering to the best of my knowledge.
1) As mentioned by hardwarefriend, synthesis tools are standard in ASIC/FPGA design flows. However, chip design currently often still takes a lot of manual work and/or stitching together of tools. The main goal of the compiler is to create a push-button solution. Designing a new chip should be as simple as cloning a design from GitHub and calling "make" on the silicon compiler.
2) Related to (1). The focus is on automation rather than performance. We are okay with sacrificing performance as long as compiler users don't have to deal with individual build steps.
3) There should be support for both digital, analog, and mixed-signal designs.
4) Rest assured that people are aware of yosys and related tools. In fact, Clifford was present at the event :-) Other (academic) open source EDA tools include the ABC for logic synthesis & verification, the EPFL logic synthesis libraries (disclaimer: co-author), and Rsyn for physicial design. There are many others, I'm certainly not familiar with all of them. Compiling a library of available open source tools is part of the project.
Edit: to be clear, WOSET has been planned, but will be held in November. Submissions are open until August 15.